求翻译：在Quartus II软件使用Verilog HDL语言设计了一个高性能改进的8位加法数乘法器，其中8位×1位乘法器可以用8 个与门实现, 最终的移位相加器是通过一个并行的加法器来实现的，也可以通过减少加法器的规模来节省了资源的消耗，同时采用了流水线技术提高了加法器的运行速度最终从整体上实现一个快速的乘法器。是什么意思？

Verilog hdl language design in quartus ii software addition the number of multipliers, a high-performance improvement of 8, 8 × 1-bit multiplier with eight doors, the final shift sum is by the addition of a parallel to achieve, can also reduce the size of the adder to save the consumption of resourc

Software used in Quartus II Verilog HDL language design of a high-performance improvement of the law of the 8-bit multipliers, the 8-bit x 1-bit multipliers can be used with a 8 door, eventually adding an offset is a parallel adder, you can also reduce the size of the law is to save the resource con

Used Verilog in the Quartus II software the HDL language to design a high performance improvement 8 addition number multiplier, 8 ×1 position multiplier might use 8 AND gate realizations, the final shifting summator was, also may through reduce the accumulator which realized through a parallel accum

In Quartus II software using Verilog HDL language design has a high performance improved of 8 bit addition number multiplication device, which 8 bit X1 bit multiplication device can with 8 a and door implementation, eventually of shift added device is by a parallel of addition device to implementati

正在翻译，请等待...