求翻译：本文从指令执行速度、所占用资源面积、布线延迟、逻辑延迟、最小时钟周期和时钟周期数等方面综合考虑,通过比较各类乘法器基于 FPGA的实现给出了仿真、 综合和验证,指出了适合我们所使用的 FPGA芯片的乘法器设计方法是什么意思？

From the command speed of execution, resource area, wiring delay, the logic delay, the minimum clock period and the number of clock cycles, and other aspects into account, simulation, synthesis and verification of fpga-based implementation is given by comparing the various types of multipliers, poin

This article from the instruction execution speed, and the resource intensive area, Cabling delay, delay, and the logic clock and the clock cycle, the number of cycles, by comparing various multipliers are based on the realization FPGA the emulation, integration and verification, and pointed out tha

This article carries out the speed from the instruction, takes the resources area, the wiring retards, logic retards, smallest aspect overall evaluations and so on clock cycle and clock periodicity, through compared each kind of multiplier to give the simulation, the synthesis and the confirmation b

Consumed resources the article from the instruction execution speed, area, logic of wiring delay, lag, minimum clock cycles and cycles, and so considered, by comparing a variety of multiplier based on FPGA implementation of given simulation, synthesis and verification, pointed out for us the design

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