|
关注：1
2013-05-23 12:21
求翻译：当 DOUT 从高电平变低电平后，PD_SCK 应输入 25 至 27 个不等的时钟脉冲是什么意思？ 待解决
 悬赏分：1
- 离问题结束还有
当 DOUT 从高电平变低电平后，PD_SCK 应输入 25 至 27 个不等的时钟脉冲
问题补充： |
|
2013-05-23 12:21:38
Dout high low pd_sck should the input ranging from 25-27 clock pulse
|
|
2013-05-23 12:23:18
When DOUT from high-level low, PD SCK should enter the 25 and 27 of the clock pulses ranging from
|
|
2013-05-23 12:24:58
After DOUT changes the low level from the high level, PD_SCK should input 25 to 27 different clock pulses
|
|
2013-05-23 12:26:38
When DOUT after high level low level, PD_SCK enter ranging from 25 to 27 of the clock
|
|
2013-05-23 12:28:18
正在翻译，请等待...
|
湖北省互联网违法和不良信息举报平台 | 网上有害信息举报专区 | 电信诈骗举报专区 | 涉历史虚无主义有害信息举报专区 | 涉企侵权举报专区
