求翻译：负责对其核心电路DLL（延迟锁相环）电路的设计、仿真、实验验证上满足整个控制接口电路在高速、低抖动、低相位噪声方面提出了新的要求。是什么意思？

Circuit responsible for its core DLL (delay locked loop) circuit design, simulation, experimental validation to meet the control interface circuit in high-speed, low jitter, low phase noise put forward new demands.

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Was responsible to its core electric circuit DLL (detention phase-locked loop) the electric circuit design, the simulation, the experiment confirms on satisfies the entire control connection electric circuit in high speed, the low vibration, the low phase noise aspect set the new request.

Responsible DLL in its core circuit (phase-delay locked loop) circuit simulation, experimental validation of design, satisfying the entire control interface circuit in high-speed, jitter, low phase noises made new demands.

Was responsible to its core electric circuit DLL (detention phase-locked loop) the electric circuit design, the simulation, the experiment confirms on satisfies the entire control connection electric circuit in high speed, the low vibration, the low phase noise aspect set the new request.