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关注：1
2013-05-23 12:21
求翻译：Once the full adder layout is created, verify that it is without any errors by doing Verify->DRC.是什么意思？ 待解决
 悬赏分：1
- 离问题结束还有
Once the full adder layout is created, verify that it is without any errors by doing Verify->DRC.
问题补充： |
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2013-05-23 12:21:38
一次全加器的布局被创建，验证，它是没有任何错误，做验证 - > DRC。
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2013-05-23 12:23:18
以下是使用的程序来模拟extraxcted布局节奏nc-verilog仿真器。 1位全加器模拟extractracted示意图如下所示。
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2013-05-23 12:24:58
一旦全加器布局被创造，核实它是没有任何错误通过做Verify->DRC。
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2013-05-23 12:26:38
Once the full adder layout is created, verify that it is without any errors by doing Verify->DRC.
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2013-05-23 12:28:18
From the extracted layout, invoke the Verilog-XL simulator by Tools->Verilog-XL
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