求翻译：由于Turbo码译码算法的复杂度较高，硬件实现时译码器所消耗的逻辑资源和存储资源较多，译码延迟较大。为了满足LTE系统高数据速率、高可靠性传输的需要，高速Turbo译码器的设计面临着巨大挑战。本课题选取基于LTE系统的并行Turbo码译码器硬件设计和实现作为研究方向，选择FPGA作为硬件设计和实现的平台，从Log-MAP算法的定点化、状态度量值递归计算中的归一化处理、迭代译码算法的并行化、并行交织器设计、关键路径优化技术等方面分析，设计实现了LTE Turbo码高速并行译码器。是什么意思？

Higher due to the complexity of the turbo decoding algorithm, implemented in hardware logic decoder consumes resources and storage resources more decoding delay. In order to meet the high data rate lte system, the need for high reliability transmission, high-speed turbo decoder design faces enormous

ciphering algorithm Turbo code because of the complexity is high, the hardware for the translator of the logical resource consumption and storage resources, decoding delay. In order to meet LTE system high-data-rate, high-reliability, high-speed transfer of Turbo translator's design is facing enormo

Because the Turbo code decoding algorithm order of complexity is high, the hardware realizes when the decoder consumes the logical resources and the memory resources are many, the decoding retards in a big way.In order to satisfy the LTE system high data rate, the redundant reliable transmission nee

Due to the high complexity Turbo decoding algorithm, implemented hardware decoder logic of consumes more resources and storage resources, decode delay larger. In order to meet LTE systems, high reliable transmission of high data rate needs high speed Turbo decoder design faces enormous challenges. T

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